1 document # sram133 rev b revised september 2008 p4c1041 high speed 256k x 16 (4 meg) static cmos ram high speed (equal access and cycle times) 10/12/15/20 ns (commercial) 12/15/20 ns (industrial/military) low power single 5.0v 10% power supply 2.0v data retention functional block diagram pin configu ration feat ures description the p4c1041 is a 262,144 words by 16 bits high-speed cmos static ram. the cmos memory requires no clocks or refreshing, and has equal access and cycle times. inputs are fully ttl-compatible. the ram operates from a single 5.0v 10% tolerance power supply. access times as fast as 10 nanoseconds permit greatly enhanced system operating speeds. cmos is utilized to reduce power consumption to a low level. the p4c1041 is a member of a family of pace ram? products offering fast access times. the p4c1041 device provides asynchronous operation with matching access and cycle times. memory loca - tions are specifed on address pins a 0 to a 17 . reading is accomplished by device selection ( ce and output enabling ( oe ) while write enable ( we ) remains high. by presenting the address under these conditions, the data in the addressed memory location is presented on the data input/output pins. the input/output pins stay in the high z state when either ce or oe is high or we is low. package options for the p4c1041 include 44-pin soj and tsop packages. easy memory expansion using ce and oe inputs fully ttl compatible inputs and outputs advanced cmos technology fast t oe automatic power down when deselected packages 44-pin soj, tsop ii soj tsop ii
p4c1041 page 2 of 10 document # sram133 rev b recommended o perating temperat ure and suppl y v oltage capacita nces (4) v cc = 5.0v, t a = 25c, f = 1.0mhz dc electrical characteristics over recommended operating temperature and supply voltage (2) maximum r atings (1) grade (2) ambient temperature gnd v cc commercial 0 - 70c 0v 5.0v 10% industrial -40 - 85c 0v 5.0v 10% military -55 - 125c 0v 5.0v 10% sym parameter value unit v cc power supply pin with respect to gnd -0.5 to 7.0 v v term terminal voltage with respect to gnd -0.5 to vcc+0.5 v t a operating temperature -55 to 125 c t bias temperature under bias -55 to 125 c t stg storage temperature -65 to 150 c i out dc output current 20 ma sym parameter conditions typ. unit c in input capacitance v in = 0v 8 pf c out output capacitance v out = 0v 8 pf sym parameter test conditions p4c1041 unit min max v ih input high voltage 2.2 v cc +0.5 v v il input low voltage -0.5 (3) 0.8 v v ol output low voltage (ttl load) i ol = +8 ma, v cc = min. 0.4 v v oh output high voltage (ttl load) i oh = C4 ma, v cc = min. 2.4 v i li input leakage current v cc = max. v in = gnd to v cc -2 +2 a i lo output leakage current v cc = max., ce = v ih , v out = gnd to v cc -1 +1 a i sb standby power supply current (ttl input levels) ce v ih v cc = max, f = max., outputs open v in v ih or v in v il 40 ma i sb1 standby power supply current (cmos input levels) ce v cc - 0.2v v cc = max, f = 0, outputs open v in v cc - 0.3v or v in 0.3v 6 ma
p4c1041 page 3 of 10 document # sram133 rev b *v cc = 3.6v. tested with outputs open. f = max. switching inputs are 0v and 3v. ce = v il , oe = v ih . power dissipatio n characteristics vs. speed ac electrical characteristicsread c ycle (v cc = 5.0v 10%, all temperature ranges) (2) sym parameter temperature range -10 -12 -15 -20 unit i cc dynamic operating current* commercial 100 90 80 70 ma industrial 100 90 80 70 ma military n/a 110 100 90 ma sym parameter -10 -12 -15 -20 unit min max min max min max min max t rc read cycle time 10 12 15 20 ns t aa address access time 10 12 15 20 ns t ac chip enable access time 10 12 15 20 ns t oh output hold from address change 3 3 3 3 ns t lz chip enable to output in low z 3 3 3 3 ns t hz chip disable to output in high z 5 6 7 8 ns t oe output enable low to data valid 5 6 7 8 ns t olz output enable low to low z 0 0 0 0 ns t ohz output enable high to high z 5 6 7 8 ns t pu chip enable to power up time 0 0 0 0 ns t pd chip disable to power down time 10 12 15 20 ns t be byte enable to data valid 5 6 7 8 ns t lzbe byte enable to low z 0 0 0 0 ns t hzbe byte disable to high z 6 6 7 8 ns
p4c1041 page 4 of 10 document # sram133 rev b timin g waveform of read cycle no. 2 ( oe controlled) (5,6) notes: 1. stresses greater than those listed under maximum r atings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to maximum rating conditions for extended periods may affect reliability. 2. extended temperature operation guaranteed with 400 linear feet per minute of air fow. 3. transient inputs with v il not more negative than C2.0v and v ih d v cc + 0.5v, are permissible for pulse widths up to 20 ns. 4. this parameter is sampled and not 100% tested. 5. we is high for read cycle. 6. ce is low and oe is low for read cycle. 7. address must be valid prior to, or coincident with ce transition low. 8. transition is measured 200 mv from steady state voltage prior to change, with loading as specifed in figure 1. this parameter is sampled and not 100% tested. 9. read cycle time is measured from the last valid address to the frst transitioning address. timin g waveform of read cycle no. 1
p4c1041 page 5 of 10 document # sram133 rev b ac characteristicswrite cycle (v cc = 5.0v 10%, all temperature ranges) (2) timin g waveform of write cycle no. 1 ( ce controlled) sym. parameter -10 -12 -15 -20 unit min max min max min max min max t wc write cycle time 10 12 15 20 ns t cw chip enable time to end of write 7 8 10 10 ns t aw address valid to end of write 7 8 10 10 ns t as address setup time to write start 0 0 0 0 ns t wp write pulse width 7 8 10 10 ns t ah address hold time 0 0 0 0 ns t dw data valid to end of write 5 6 7 8 ns t dh data hold time 0 0 0 0 ns t wz write enable to output in high z 5 6 7 8 ns t ow output active from end of write 5 5 0 0 ns t lzwe we high to low z 3 3 3 3 ns t bw byte enable to end of write 7 8 10 10 ns
p4c1041 page 6 of 10 document # sram133 rev b timing w aveform of write cycle no. 2 ( ble or bhe controlled) timing w aveform of write cycle no. 3 ( we controlled, oe low)
p4c1041 page 7 of 10 document # sram133 rev b ac test conditions figure 1. output load figure 2. thevenin equivalent * including scope and test fxture. note: because of the ultra-high speed of the p4c1041, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. long high-inductance leads that cause supply bounce must be avoided by bringing the v cc and ground planes directly up to the contactor fngers. a 0.01 f high frequency capacitor is also required between v cc and ground. to avoid signal refections, proper termination must be used; for example, a 50 test environment should be terminated into a 50 load with 1.73v (thevenin voltage) at the comparator input, and a 116 resistor must be used in series with d out to match 166 (thevenin resistance). tru th table input pulse levels gnd to 3.0v input rise and fall times 3ns input timing reference level 1.5v output timing reference value 1.5v output load see figures 1 & 2 mode ce oe we ble bhe i/o 0 - i/o 7 i/o 8 - i/o 15 power powerdown h x x x x high z high z standby read all bits l l h l l d out d out active read lower bits only l l h l h d out high z active read upper bits only l l h h l high z d out active write all bits l x l l l d in d in active write lower bits only l x l l h d in high z active write upper bits only l x l h l high z d in active selected, outputs disabled l h h x x high z high z active
p4c1041 page 8 of 10 document # sram133 rev b ordering in formation
p4c1041 page 9 of 10 document # sram133 rev b soj small o utlin e ic package tsop ii thi n small outlin e package pkg # t2 # pins 44 symbol min max a 0.039 0.047 a 2 0.033 0.045 b 0.012 0.016 d 0.396 0.404 e 0.721 0.729 e 0.0315 bsc h d 0.462 0.470 pkg # j8 # pins 44 (400 mil) symbol min max a 0.128 0.148 a1 0.082 - b 0.013 0.023 c 0.007 0.013 d 1.120 1.130 e 0.050 bsc e 0.435 0.445 e1 0.395 0.405 e2 0.370 bsc q 0.025 -
p4c1041 page 10 of 10 document # sram133 rev b revisions document number sram 133 document title p4c1041 high speed 256k x 16 (4 meg) static cmos ram rev issu e date origin ator description of change or jan-2007 jdb new data sheet a july-2008 jdb added military processing, lead-free designation b sept-2009 jdb updated tsop ii package drawing
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